Field
Embodiments of the present invention generally relate to methods for forming fin structures with desired materials on a semiconductor substrate, and more particularly to methods for forming fin structures on a semiconductor substrate utilizing a conversion process to convert the fin structure to have a desired material fin field effect transistor (FinFET) semiconductor manufacturing applications.
Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. In particular, fin field effect transistors (FinFET) are often utilized to form three dimensional (3D) stacking of semiconductor chips. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been widely used in many logic and other applications and are integrated into various different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the fin devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reducing the short channel effect and providing higher current flow.
FIG. 1A depicts an exemplary embodiment of a fin field effect transistor (FinFET) 150 disposed on a substrate 100. The substrate 100 may be a silicon substrate, a germanium substrate, or a substrate formed from other semiconductor materials. In one embodiment, the substrate 100 may include p-type or n-type dopants doped therein. The substrate 100 includes a plurality of semiconductor fins 102 formed thereon isolated by shallow trench isolation (STI) structures 104. The shallow trench isolation (STI) structures 104 may be formed by an insulating material, such as a silicon oxide material, a silicon nitride material or a silicon carbon nitride material.
The substrate 100 may include a portion in NMOS device region 101 and a portion in PMOS device region 103 as needed, and each of the semiconductor fins 102 may be sequentially and alternatively formed in the NMOS device region 101 and the PMOS device region 103 in the substrate 100. The semiconductor fins 102 are formed protruding above the top surfaces of the shallow trench isolation (STI) structures 104. Subsequently, a gate structure 106, typically including a gate electrode layer disposed on a gate dielectric layer, is deposited on both of the NMOS device region 101 and the PMOS device region 103 and over the semiconductor fins 102.
The gate structure 106 may be patterned to expose portions 148, 168 of the semiconductor fins 102, 152 uncovered by the gate structure 106. The exposed portions 148, 168 of the semiconductor fins 102 may then be doped with dopants to form lightly doped source and drain (LDD) regions using an implantation process.
FIG. 1B depicts a cross sectional view of the substrate 100 including the plurality of semiconductor fins 102 formed on the substrate 100 isolated by the shallow trench isolation (STI) structures 104. The plurality semiconductor fins 102 formed on the substrate 100 may be part of the substrate 100 extending upwards from the substrate 100 utilizing the shallow trench isolation (STI) structures 104 to isolate each of the semiconductor fins 102. In another embodiment, the semiconductor fins 102 may be individually formed structures disposed on the substrate 100 that are made from materials different than the substrate 100 using suitable techniques available in the art. In the embodiment wherein different materials of the semiconductor fins 102 are required, additional process steps may be performed to replace or alter the materials of the semiconductor fins 102 formed from the substrate 102.
Germanium containing material, such as SiGe containing material or Ge alloys, group III-V materials or other compound materials are often selected to be doped into the semiconductor fin 102 or to manufacture the structures of the semiconductor fins 102 on the substrate for different device performance requirements. In one example, SiGe or Ge dopants are often used to form the semiconductor fin 102 to improve the device performance.
However, as the designs of the three dimensional (3D) stacking of fin field effect transistor (FinFET) 150 are pushed up against the technology limits for the structure geometry, the need for accurate process control for the manufacture of semiconductor fins 102 on the substrate 100 has become increasingly important. Conventional processes for manufacturing composite materials for the semiconductor fin 102 often suffer from high cost, complicated process steps, poor dopant concentration control, poor profile control and difficult thermal budget control, thereby resulting in resulting in inaccurate semiconductor fin profile control, poor dimension control and undesired defect formation. Furthermore, conventional process for forming the semiconductor fin 102 with Ge compounds, such as Ge-on-insulator (GeOI) process, often requires multiple complicated process sequences and steps to complete the process, which may adversely cause high manufacture cost, cycle time, and high doping dose and extra long doping time.
Thus, there is a need for improved methods for forming semiconductor fin structure with different materials on a substrate with good profile and dimension control for three dimensional (3D) stacking of semiconductor chips or other semiconductor devices.